Since the first computer was built, computer engineers have searched for ways to increase the speed and power of computer systems. One method that is now being used for improving system performance is to utilize multiple processors in a single system. In such a system, there is typically a master or primary processor which performs certain processing tasks and sends other processing tasks to the slaves or coprocessors. The processors typically operate asynchronously. An example of such a system is a multi-processor system utilizing a scalar processor as the primary processor and a vector processor as a coprocessor. In operation of the system, the scalar processor transfers vector instructions, comprised of an opcode and a variable number of operands, to the vector processor. Since the two processors are operating asynchronously, the scalar processor continues its processing tasks while the vector processor simultaneously processes the vector instructions. This method of operation results in faster execution of a stored computer program comprised of a mix of vector and non-vector type instructions over an otherwise equivalent system employing only one processor.
However, the desired increase in operating speed and processing power of the overall system can be severely limited by the method or protocol used for inter-processor communications. The coprocessor cannot begin the execution of an instruction before it has been completely transferred. Accordingly, the primary processor must be able to transfer instructions to the coprocessor both quickly and reliably. An instruction is comprised of a set of data words which includes an opcode and a variable number of operands. The number of operands may range from zero to many. The data word containing the opcode may also contain other information, including all or part of an operand. However, as used herein, "opcode" refers to the entire data word containing the opcode and the term "operands" refers to the data words which are part of the instruction but which do not contain the opcode. Thus, a complete instruction transfer actually requires a series of transfers in most cases. This series of transfers should be accomplished at a speed which results in an increase in overall system performance. Otherwise, there is little advantage to the employment of coprocessors in the system.
Known methods of communication between asynchronous processors typically utilize parallel, "fully-handshaked" protocols over a bus interconnecting the processors. A fully-handshaked protocol requires that each processor positively acknowledge each step of every transfer on the bus. In this type of protocol, an instruction transfer is accomplished by sequentially transferring the data word containing the opcode followed by each associated operand. This is accomplished by the primary processor first asserting a strobe signal, to indicate the start of a bus transaction, and at the same time transmitting the opcode of the instruction to be transferred. When the strobe signal and opcode are received by the coprocessor, it responds with an acknowledgement signal. This signal indicates to the primary processor that the opcode has been received (or latched) by the coprocessor. Upon recognizing the acknowledgement, the primary processor deasserts the strobe. When the coprocessor recognizes the deassertion of the strobe, it deasserts the acknowledge signal. When the primary processor recognizes the deassertion of the acknowledgment signal, the handshake is complete, and the bus is available for the next transaction. This sequence of steps is repeated in order to transfer each operand associated with the previously transferred opcode until the entire instruction has been transferred.
In a system utilizing a fully-handshaked protocol for instruction transfers between asynchronous processors, each processor operates on its own time base and there is no time base for the bus. Therefore, signals asserted by one processor are not received immediately by the other processor since the signals on the bus must be held until the receiving processor's internal timing allows the signals to be latched.
Accordingly, the performance of a fully-handshaked protocol is likely to detract from overall system performance. Poor performance of this protocol results from a combination of synchronization delays incurred each time either processor transmits a signal to be received by the other processor and from the numerous transmissions which must be sent and received to complete an instruction transfer.
It would, therefore, be desirable and advantageous to employ a method of transferring instructions between asynchronous processors which is reliable and which requires only one acknowledge signal from the receiving processor for each instruction transferred regardless of the number of operands associated with the instruction.